So it has been a while since my last CUPC/8 (formerly known as CUPCake) update.

Over the past few months I have spent a significant amount of time working fleshing out the instruction set, implementing support in the assembler and simulator and coding the Kernel (the status of which will be discussed in another blog post).

I have also spent some time back with the hardware itself; integrating and testing the physical RAM and MMU FPGA modules, bus interfaces etc.

Additionally, I finally got around to starting the documentation (see here). Some of it is already slightly out of date but hopefully I'll revise it soon.

As development has progressed, I have continually challenged my original design decisions and this has resulted in a few design revisions.

The main change is that the memory board is no longer responsible for loading the ROM into primary memory on boot. It just didn't make sense for me to use a powerful (relative to CUPC/8) XMEGA MCU within the context of the project as a whole.
As such, I have removed the XMEGA from the design. The ROM chip is now connected directly the the SoC over I2C. The SoC also now includes a small ROM buffer on-chip (termed ROM0) which will hold code that will be responsible for bootstrapping the ROM code. ROM0 is memory-mapped into the 64k memory region by the MMU. The hard reset vector points to the start of the ROM0 and will therefore execute it on boot.
The ROM0 code will be minimal; consiting of a stripped-down I2C driver responsible for the loading of the off-chip ROM chip (ROM1) into primary memory and jumping to the ROM1 start vector.
This is somewhat similar to how modern CPUs bootstrap today.

My next milestone is to get the hardware SPI and I2C modules working properly and interfacing ROM1 with the FPGA development board.