So, it turns out that the first memory board is totally insufficient.
Well, I guess it's a good SRAM board, but what about ROM?!
The second attempt on the board uses a single Alliance AS6C1008 which is a 128kx8 chip. As CUPC/8 address bus is 16-bit wide, we'd need bank switching to make full use of the upper 64k, but this is disabled (tied to ground) on the board for now.
ROM is provided by a I2C EEPROM chip. A microcontroller (XMEGA) is used to load the ROM into SRAM on poweron. The idea is that on boot CUPC/8's CPU address and data lines will be in high impedance state and the MCU will have control over the SRAM. Once the ROM is copied over, the MCU will flick it's outputs to high-Z, signal the CPU and put itself in a low-power state. The MCU is also used as a way to program the E2 in-circuit over UART.
I've still to code up the XMEGA MCU software so the board is completely untested. I don't even have the XMEGA chips or a programmer yet (Farnell order is on it's way)!
BoM:
Schematic:
